
/*
 * (C) Copyright 2009, HISILICON
 * Configuation settings for the godeyes board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <asm/arch/platform.h>
#include <asm/arch/ddrc.h>

#ifndef __CONFIG_GODEYES_H__
#define __CONFIG_GODEYES_H__
/****************************************/

/***************************************/
/* Arm configuration*/
#define CONFIG_L2_OFF  

/* cpu_init configuration */
#define HW_REG(a) *(volatile unsigned int *)(a)
#define A9_AXI_SCALE_REG   0X20030020
#define get_bus_clk()({\
        unsigned long fbdiv,pstdiv1,pstdiv2,refdiv; \
        unsigned long tmp_reg,foutvco,busclk;\
        tmp_reg = HW_REG(REG_CRG0_OFFSET);\
        pstdiv1 = (tmp_reg >> 24) & 0x7;\
        pstdiv2 = (tmp_reg >> 27) & 0x7;\
        tmp_reg = HW_REG(REG_CRG1_OFFSET);\
        refdiv = (tmp_reg >> 12) & 0x3f;\
        fbdiv = tmp_reg & 0xfff;\
        foutvco = 24000000/refdiv;\
        foutvco *= fbdiv;\
        tmp_reg = HW_REG(A9_AXI_SCALE_REG);\
	if((tmp_reg & 0x1) ==0 ){\
	        busclk = foutvco/4;\
	}else{\
		busclk = foutvco/6;\
	}\
	busclk;\
})

/* cpu_init configuration */
#define CFG_CLK_BUS  get_bus_clk()
#define CFG_TIMER_PER 2
#define CFG_TIMER_CLK (CFG_CLK_BUS/CFG_TIMER_PER)
//#define CFG_TIMER_CLK (50000000/CFG_TIMER_PER)

/*-----------------------------------------------------------------------
 * SPI Flash Configuration
 -----------------------------------------------------------------------*/
#define CONFIG_SPI_FLASH_HISFC300               1
#define CFG_SF_BASE (0x58000000)
#define CONFIG_CMD_SF	  /*sf read \ sf write \ sf erase */
#define SFC_MEM_BASE CFG_SF_BASE
#define SFC_REG_BASE 0x10010000
#define REG_BASE_CRG 0x20030000
#define CONFIG_HISFC300_BUFFER_BASE_ADDRESS SFC_MEM_BASE
#define CONFIG_HISFC300_REG_BASE_ADDRESS SFC_REG_BASE
#define CONFIG_HISFC300_PERIPHERY_REGBASE REG_BASE_CRG
#define CONFIG_HISFC300_CHIP_NUM 2
/*-----------------------------------------------------------------------
 * for cpu/arm_cortexa9/start.S 
 -----------------------------------------------------------------------*/
#define MEM_BASE_BOOTRAM 0
#define MEM_SIZE_BOOTRAM 0x10000
#define NAND_TEXT_ADRS      (CONFIG_SYS_NAND_BASE)
#define SF_TEXT_ADRS        (CFG_SF_BASE)
#define MEM_BASE_DDR	    (DDR_MEM_BASE)	
#define CONFIG_SYS_MALLOC_LEN      (CONFIG_ENV_SIZE + 128*1024)
#define CONFIG_SYS_GBL_DATA_SIZE   128     /* size in bytes reserved for initial data */

/*-----------------------------------------------------------------------
 * for timer configuration (udelay) 	cpu/godeyes/godeyes/timer.c
*  enable timer				board/godeyes/board.c 
 -----------------------------------------------------------------------*/
#define CFG_TIMERBASE           TIMER0_REG_BASE 
#define CFG_TIMER_CTRL          0xCA //enable timer.32bit, periodic,mask irq,256 divider.
#define READ_TIMER      	(*(volatile unsigned long *)(CFG_TIMERBASE + REG_TIMER_VALUE))
#define CONFIG_SYS_HZ           (CFG_TIMER_CLK/256)//how many ticks per second. show the precision of timer.
#define CFG_HZ			CONFIG_SYS_HZ
/*system boot sel*/
//#define SYS_CTRL_BASE   (0x101f5000)
#define SYS_CTRL_BASE   (0x20050000)
#define START_MODE      (0x8c)

/*allow change env*/
#define  CONFIG_ENV_OVERWRITE
/*-----------------------------------------------------------------------
 * environment && bd_info  && global_data  configure
*     used in file
-----------------------------------------------------------------------*/
#define CONFIG_ENV_IS_IN_NAND     1            /* env in flash instead of CFG_ENV_IS_NOWHERE */
#define CONFIG_ENV_IS_IN_SPI_FLASH     1            /* env in flash instead of CFG_ENV_IS_NOWHERE */
#define CONFIG_ENV_OFFSET          0x80000      /* environment starts here  */
//llz for debug, env store to nand flash.
#define CONFIG_ENV_NAND_ADDR       (CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SPI_ADDR        (CONFIG_ENV_OFFSET)
#define CONFIG_CMD_SAVEENV     

#define CONFIG_ENV_SIZE            0x40000    /*include ENV_HEADER_SIZE */
#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
#define CONFIG_NR_DRAM_BANKS       1          /* we have 1 bank of DRAM */
#define CFG_BOOT_PARAMS            (MEM_BASE_DDR+0x0100)	//kernel parameter list phy addr

/*-----------------------------------------------------------------------
 *  Environment   Configuration
 ------------------------------------------------------------------------*/
#define CONFIG_BOOTDELAY    1
#define CONFIG_BOOTARGS "mem=64M console=ttyAMA0,115200"
#define CONFIG_NETMASK  255.255.255.0       /* talk on MY local net */
#define CONFIG_IPADDR   192.168.1.10        /* static IP I currently own */
#define CONFIG_SERVERIP 192.168.1.1     /* current IP of tftp server ip */
#define CONFIG_ETHADDR  00:00:23:34:45:66
#define CONFIG_MDIO_INTF "rgmii"
#define CONFIG_BOOTFILE "uImage"        /* file to load */
#define CONFIG_BAUDRATE         115200
/*-----------------------------------------------------------------------
 * for bootm linux 
*  used in file  board/godeyes/board.c
 -----------------------------------------------------------------------*/

#define CONFIG_BOOTM_LINUX 1    //for bootm
#define CONFIG_SYS_LOAD_ADDR (CFG_DDR_PHYS_OFFSET + 0x08000)   /* default load address 0x80008000*/
#define CONFIG_ZERO_BOOTDELAY_CHECK 1   /*use ^c to interrupt*/
 
/*-----------------------------------------------------------------------
 * for  commond configure 
 -----------------------------------------------------------------------*/
//tftp comm
#define CONFIG_TFTP_TSIZE

//do_printenv  do_setenv common/cmd_nvedit.c
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_MAXARGS 16          /* max number of command args   */


//#define CONFIG_CMD_SF	  /*sf read \ sf write \ sf erase */
#define CONFIG_CMD_LOADB  /* loadb   common/cmd_load.c*/ 

/* higmac */
#define CONFIG_NET_HIGMAC
#define CONFIG_ARP_TIMEOUT		50000UL//FIXME
#define CONFIG_NET_RETRY_COUNT		50//FIXME
#define CONFIG_CMD_NET 
#define CONFIG_CMD_PING /* do_ping common/cmd_net.c*/
#define CONFIG_CMD_MII
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1

//nand flash
#define CONFIG_SYS_64BIT_VSPRINTF
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x50000000 
#define CONFIG_NAND_GODEYES 1
#define CFG_MAX_NAND_DEVICE CONFIG_SYS_MAX_NAND_DEVICE 
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2

#define CONFIG_HINFC301_MAX_CHIP CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_HINFC301_REG_BASE_ADDRESS 0x10000000
#define CONFIG_HINFC301_BUFFER_BASE_ADDRESS 0x50000000
#define CONFIG_HINFC301_HARDWARE_PAGESIZE_ECC 

//no nor flash
#define CONFIG_SYS_NO_FLASH
// cp.b 
#define CONFIG_CMD_MEMORY  /*md mw cp etc.*/

/*-----------------------------------------------------------------------
 * console display  Configuration
 ------------------------------------------------------------------------*/

#define CONFIG_VERSION_VARIABLE  1 /*used in common/main.c*/
#define CONFIG_SYS_PROMPT  "hisilicon # "        /* Monitor Command Prompt   */
#define CONFIG_SYS_CBSIZE  1024            /* Console I/O Buffer Size  */
#define CONFIG_SYS_PBSIZE  (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)

#define CFG_LONGHELP
#define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
#undef  CFG_CLKS_IN_HZ              /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR   (CFG_DDR_PHYS_OFFSET + 0x08000)     /* default load address */
#define CONFIG_AUTO_COMPLETE    1
#define CFG_CMDLINE_HISTORYS    8
#define CONFIG_CMDLINE_EDITING
#define CFG_DDR_PHYS_OFFSET MEM_BASE_DDR
//#define CFG_DDR_SIZE        ((0x800000<<CFG_DDRC_CHIPCAP) * ((16<<CFG_DDRC_BUSWITH)/(8<<CFG_DDRC_CHIPBITS)))
#define CFG_DDR_SIZE		(1024*1024*1024) 

#define CONFIG_SYS_MEMTEST_START       (CFG_DDR_PHYS_OFFSET + sizeof(unsigned long))
#define CONFIG_SYS_MEMTEST_END         (CFG_DDR_PHYS_OFFSET + CFG_DDR_SIZE)
#define CONFIG_SYS_MEMTEST_SCRATCH     CFG_DDR_PHYS_OFFSET

#define CONFIG_CMDLINE_TAG      1   /* enable passing of ATAGs  */
#define CONFIG_INITRD_TAG       1   /* support initrd */
#define CONFIG_SETUP_MEMORY_TAGS    1
#define CONFIG_MISC_INIT_R      1   /* call misc_init_r during start up */

#define CONFIG_ETHADDR_TAG	1
#ifdef  CONFIG_ETHADDR_TAG
#define CONFIG_ETHADDR_TAG_VAL	0x726d6d73
#endif

#define CONFIG_ETHMDIO_INF     1
#ifdef  CONFIG_ETHMDIO_INF
#define CONFIG_ETH_MDIO_INF_TAG_VAL 0x726d6d74
#endif

//driver
#define CONFIG_PL011_SERIAL 1
#define CONFIG_PL011_CLOCK  (CFG_CLK_BUS/2)
//#define CONFIG_PL011_CLOCK  (50000000/2)
#define CFG_SERIAL0	UART0_REG_BASE 
#define CFG_SERIAL1     UART1_REG_BASE 
#define CFG_SERIAL2     UART2_REG_BASE 
#define CFG_SERIAL3     UART3_REG_BASE 
#define CONFIG_PL01x_PORTS  { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 , (void *)CFG_SERIAL1 , (void *)CFG_SERIAL1}
#define CONFIG_CONS_INDEX   0


#endif	/* __CONFIG_H */

